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rev. 1.0 september 1999 1/125 this is preliminary information on a new product in development or undergoing evaluation. details are subject to change without notice. st72334j/n, st72314j/n, st72124j 8-bit mcu with single voltage flash memory, adc, 16-bit timers, spi, sci interfaces product preview n 8k or 16k program memory (rom or single voltage flash) with read-out protection n 256-bytes eeprom data memory n in-situ programming (remote isp) n enhanced reset system n low voltage supply supervisor with 3 programmable levels n low consumption resonator or rc oscillators and by-pass for external clock source, with safe control capabilities n 4 power saving modes n standard interrupt controller n 44 or 32 multifunctional bidirectional i/o lines: external interrupt capability (4 vectors) 21 or 19 alternate function lines 12 or 8 high sink outputs n real time base, beep and clock-out capabilities n configurable watchdog reset n two 16-bit timers with: 2 input captures (only one on timer a) 2 output compares (only one on timer a) external clock input on timer a pwm and pulse generator modes n spi synchronous serial interface n sci asynchronous serial interface n 8-bit adc with 8 input pins (6 only on st72334jx, not available on st72124j2) n 8-bit data manipulation n 63 basic instructions n 17 main addressing modes n 8 x 8 unsigned multiply instruction n true bit manipulation n full hardware/software development package device summary tqfp44 10x10 psdip42 psdip56 tqfp64 14 x 14 features st72124j2 st72314j2 st72314j4 st72314n2 st72314n4 st72334j2 st72334j4 st72334n2 st72334n4 program memory - bytes 8k 8k 16k 8k 16k 8k 16k 8k 16k ram (stack) - bytes 384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) eeprom - bytes - - - -- 256 256 256 256 peripherals watchdog, 16-bit tim- ers, spi, sci watchdog, 16-bit timers, spi, sci, adc operating supply 3.0v to 5.5v cpu frequency 500 khz to 8 mhz (with 1 to 16 mhz oscillator) operating temperature -40 cto+85 c (-40 c to +105/125 c optional) packages tqfp44 / sdip42 tqfp64 / sdip56 tqfp44 / sdip42 tqfp64 / sdip56 1
table of contents 125 2/125 2 1 preamble: st72c334 versus st72e331 specification . . . . . . . . . . . . . ............ 5 2 general description . . . . . . ................................................ 6 2.1 introduction . . . . . . . . . . . . . ............................................ 6 2.2 pin description . . ..................................................... 7 2.3 register & memory map . . . ........................................... 12 2.4 flash program memory . . . . . . . . . . . . .................................. 16 2.4.1 introduction . . . .................................................... 16 2.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.3 structural organisation . . . . . . . . . . . . . . ............................. .... 16 2.4.4 in-situ programming (isp) mode . . . . . .................................. 16 2.5 program memory read-out protection . . . . . . . . . . . . . . . . . . . ........... 16 2.6 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 17 2.6.1 introduction . . . .................................................... 17 2.6.2 main features . . . . . . ........................................... .... 17 2.6.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 18 2.6.4 data eeprom and power saving modes . . . . . . . . . . . . . ................... 19 2.6.5 data eeprom access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.6.6 register description . . . . . . ........................................... 20 3 central processing unit . . ............................................... 21 3.1 introduction . . . . . . . . . . . . . ........................................... 21 3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . .............................. 21 3.3 cpu registers . . . .................................................... 21 4 supply, reset and clock management . . . . ................................ 24 4.1 low voltage detector (lvd) . . . . . . . . . . . . . . ........................... 25 4.2 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 26 4.3 clock security system (css) . . . . . .................................... 32 4.3.1 clock filter control . . ........................................... .... 32 4.3.2 safe oscillator control . . . . ........................................... 32 4.4 supply, reset and clock register description . . . . . . . . . . . . . . . . . . . . . . 33 4.5 main clock controller (mcc) . . . . ................................ .... 34 5 interrupts & power saving modes . . . . . . . ............................. .... 36 5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 38 5.2.1 introduction . . . .................................................... 38 5.2.2 halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 38 5.2.3 wait mode ....................................................... 40 5.2.4 slow mode . . . . . . . . . . . . . . . . . . . . . . . . .............................. 41 6 on-chip peripherals . . . . . . . . . . . ........................................... 42 6.1 i/o ports . . . . . . . . . . . . . . . . . . ........................................... 42 6.1.1 introduction . . . .................................................... 42 6.1.2 functional description . . . . ........................................... 42 6.1.3 i/o port implementation . . . . . . . . . . . . . . . . . . . ........................... 44 6.1.4 register description . . . . . . ........................................... 45 6.2 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2.1 i/o port interrupt sensitivity description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
table of contents 3/125 3 6.2.2 i/o port alternate functions ........................................... 47 6.2.3 miscellaneous registers description .................................... 48 6.3 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.1 introduction . . . .................................................... 50 6.3.2 main features . . . . . . ........................................... .... 50 6.3.3 functional description . . . . ........................................... 50 6.3.4 hardware watchdog option . . . . . . . . . . ................................. 51 6.3.5 low power modes . . . ............................................... 51 6.3.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 51 6.3.7 register description . . . . . . ........................................... 51 6.4 16-bit timer . . . . . . . . . . . . . . . . . . ........................................ 53 6.4.1 introduction . . . .................................................... 53 6.4.2 main features . . . . . . ........................................... .... 53 6.4.3 functional description . . . . ........................................... 53 6.4.4 low power modes . . ............................................... 64 6.4.5 interrupts . . . . . ................................. ................... 64 6.4.6 register description . . . . . . ........................................... 65 6.5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . ........... 70 6.5.1 introduction . . . .................................................... 70 6.5.2 main features . . . . . . ........................................... .... 70 6.5.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.5.4 functional description . . . . ........................................... 72 6.5.5 low power modes . . . ............................................... 79 6.5.6 interrupts . . . . . ................................. ................... 79 6.5.7 register description . . . . . . ........................................... 80 6.6 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.6.1 introduction . . . .................................................... 83 6.6.2 main features . . . . . . ........................................... .... 83 6.6.3 general description . . . . . . ........................................... 83 6.6.4 functional description . . . . ........................................... 85 6.6.5 low power modes . . . ............................................... 90 6.6.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 90 6.6.7 register description . . . . . . ........................................... 91 6.7 8-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . ........................... 95 6.7.1 introduction . . . .................................................... 95 6.7.2 main features . . . . . . ........................................... .... 95 6.7.3 functional description . . . . ........................................... 95 6.7.4 low power modes . . . ............................................... 96 6.7.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 96 6.7.6 register description . . . . . . ........................................... 97 7 instruction set . . . . . . . . . . . . . . . . . . ........................................ 99 7.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.1.1 inherent . . . . . . . . . . . .............................................. 100 7.1.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.1.3 direct . .......................................................... 100 7.1.4 indexed (no offset, short, long) . . . . . . . . . . . . .......................... 100 7.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.1.6 indirect indexed (short, long) . ....................................... 101
table of contents 125 4/125 7.1.7 relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.2 instruction groups . . . . . . . . . . . . . . . . ................................ 102 8 electrical characteristics . . . . . . . . . . . . . . . . ............................. 105 8.1 absolute maximum ratings . . . ....................................... 105 8.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .......... 107 8.4 general timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 107 8.5 i/o port characteristics . .......... ................................. 108 8.6 supply, reset and clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.1 supply manager ................................................... 109 8.6.2 reset sequence manager . . . ........................................ 109 8.6.3 multi-oscillator, clock security system . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 109 8.7 memory and peripheral characteristics . . . . . . . . ................... 111 9 general information . . . . . . . . . . .......................................... 117 9.1 packages . . . . . . . . . . . . . . . . . .......................................... 117 9.1.1 package mechanical data . . . . . . . . . . ................................. 117 9.1.2 user-supplied tqfp64 adaptor / socket . . . . . . .......................... 119 9.1.3 user-supplied tqfp44 adaptor / socket . . . . . . .......................... 120 9.2 device configuration and ordering information . . . . . .............. 121 9.2.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . ............................. 121 9.2.2 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . .............. 122 10 summary of changes . .................................................. 124
table of contents 5/125 1 preamble: st72c334 versus st72e331 specification new features available on the st72c334 n 8 or 16k flash/rom with in-situ programming and read-out protection n new adc with a better accuracy and conversion time n new configurable clock, reset and supply system n new power saving mode with real time base: active halt n beep capability on pf1 n new interrupt source: clock security system (css) or main clock controller (mcc) st72c334 i/o confuguration and pinout n same pinout as st72e331 n pa6 and pa7 are true open drain i/o ports without pull-up (same as st72e331) n pa3, pb3, pb4 and pf2 have no pull-up configuration (all ios present on tqfp44) n pa5:4, pc3:2, pe7:4 and pf7:6 have high sink capabilities (20ma on n-buffer, 2ma on p-buffer and pull-up). on the st72e331, all these pads (except pa5:4) were 2ma push-pull pad without high sink capabilities. pa4 and pa5 were 20ma true open drain. new memory locations in st72c334 n 20h: miscr register becomes miscr1 register (naming change) n 29h: new control/status register for the mcc module n 2bh: new control/status register for the clock, reset and supply control. this register replaces the wdgsr register keeping the wdogf flag compatibility. n 40h: new miscr2 register 4
st72334j/n, st72314j/n, st72124j 6/125 2 general description 2.1 introduction the st72334j/n, st72314j/n and st72124j de- vices are members of the st7 microcontroller fam- ily. they can be grouped as follows: st72334j/n devices are designed for mid-range applications with data eeprom, adc, spi and sci interface capabilities. st72314j/n devices target the same range of applications but without data eeprom. st72124j devices are for applications that do not need data eeprom and the adc peripher- al. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. the st72c334j/n, st72c314j/n and st72c124j versions feature single-voltage flash memory with byte-by-byte in-situ pro- gramming (isp) capability. under software control, all devices can be placed in wait, slow, active-halt or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. figure 1. device block diagram 8-bit core alu address and data bus reset port b timer b port c spi port e sci port f timer a watch dog internal clock control ram (384 or 512 bytes) port d 8-bit adc port a v ssa v dda data-eeprom (256 bytes) and lvd pc7:0 v ss v dd power supply program (8 or 16k bytes) memory osc1 osc2 multi osc + clock filter v pp /tes t (8 bits) pf7,6,4,2:0 (6 bits) pe7:0 (6 bits for n versions) (2 bits for j versions) pd7:0 (8 bits for n versions) (6 bits for j versions) pa7:0 (8 bits for n versions) (5 bits for j versions) pb7:0 (8 bits for n versions) (5 bits for j versions) 5
st72334j/n, st72314j/n, st72124j 7/125 2.2 pin description figure 2. 64-pin tqfp package pinout (n versions) v dda v ssa v dd_3 v ss_3 mco / pf0 beep / pf1 pf2 nc ocmp1_a / pf4 nc icap1_a / (hs) pf6 extclk_a / (hs) pf7 ain4 / pd4 ain5 / pd5 ain6 / pd6 ain7 / pd7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei2 ei3 ei0 ei1 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 (hs) pe4 (hs) pe5 (hs) pe6 (hs) pe7 pa1 pa0 pc7 / ss pc6 / sck / ispclk pc5 / mosi pc4 / miso / ispdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b pc0 / ocmp2_b v ss_0 v dd_0 v ss_1 v dd_1 pa3 pa2 v dd _2 osc1 osc2 v ss _2 nc nc reset ispsel pa7 (hs) pa6 (hs) pa5 (hs) pa4 (hs) nc nc pe1 / rdi pe0 / tdo 6
st72334j/n, st72314j/n, st72124j 8/125 pin description (cont'd) figure 3. 56-pin sdip package pinout (n versions) 52 51 50 49 48 47 46 45 44 43 42 41 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 53 54 55 56 pb4 pb5 beep / pf1 mco / pf0 v ssa v dda ain7 / pd7 ain6 / pd6 ain5 / pd5 ain2 / pd2 ain1 / pd1 ain0 / pd0 pb7 pb6 ain4 / pd4 ain3 / pd3 pb3 pb2 ispsel reset v ss _2 osc2 osc1 v dd _2 pe0 / tdo pe5 (hs) pe6 (hs) pe7 (hs) pb0 pb1 pe4 (hs) pe1 / rdi ei3 ei0 ei2 ei1 21 20 17 18 19 v dd_0 extclk_a / (hs) pf7 icap1_a / (hs) pf6 ocmp1_a / pf4 pf2 40 39 38 37 36 v ss_1 pa4 (hs) pa5 (hs) pa6 (hs)i pa7 (hs) 23 22 ocmp2_b / pc0 v ss_0 28 27 24 25 26 mosi / pc5 ispdata/ miso / pc4 icap1_b / (hs) pc3 icap2_b / (hs) pc2 ocmp1_b / pc1 35 34 pa3 v dd_1 33 32 31 30 29 pc6 / sck / ispclk pc7 / ss pa0 pa1 pa2
st72334j/n, st72314j/n, st72124j 9/125 pin description (cont'd) figure 4. 44-pin tqfp and 42-pin sdip package pinouts (j versions) mco / pf0 beep / pf1 pf2 ocmp1_a / pf4 icap1_a / (hs) pf6 extclk_a / (hs) pf7 v dd_0 v ss_0 ain5 / pd5 v dda v ssa 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 ei2 ei3 ei0 ei1 pb3 pb4 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 ain4 / pd4 pe1 / rdi pb0 pb1 pb2 pc6 / sck / ispclk pc5 / mosi pc4 / miso / ispdata pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b pc0 / ocmp2_b v ss_1 v dd_1 pa3 pc7 / ss v ss _2 reset ispsel pa7 (hs) pa6 (hs) pa5 (hs) pa4 (hs) pe0 / tdo v dd _2 osc1 osc2 38 37 36 35 34 33 32 31 30 29 28 27 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 39 40 41 42 pb4 ain0 / pd0 ocmp2_b / pc0 extclk_a / (hs) pf7 icap1_a / (hs) pf6 ocmp1_a / pf4 pf2 beep / pf1 mco / pf0 ain5 / pd5 ain4 / pd4 ain3 / pd3 ain2 / pd2 ain1 / pd1 v ssa v dda pb3 pb2 pa4 (hs) pa5 (hs) pa6 (hs) pa7 (hs) ispsel reset v ss _2 v dd _2 pe0 / tdo pe1 / rdi pb0 pb1 osc1 osc2 ei3 ei0 ei2 ei1 21 20 17 18 19 mosi / pc5 ispdata / miso / pc4 icap1_b / (hs) pc3 icap2_b/ (hs) pc2 ocmp1_b / pc1 26 25 24 23 22 pc6 / sck / ispclk pc7 / ss pa3 v dd_1 v ss_1
st72334j/n, st72314j/n, st72124j 10/125 pin description (cont'd) legend / abbreviations: type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd , c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = high sink (on n-buffer only), port configuration capabilities: input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog output: od = open drain, t = true open drain, pp = push-pull note: the reset configuration of each pin is shown in bold. table 1. device pin description pin n pin name type level port main function (after reset) alternate function tqfp64 sdip56 qfp44 sdip42 input output input output float wpu int ana od pp 1 49 pe4 (hs) i/o c t hs x x x x port e4 2 50 pe5 (hs) i/o c t hs x x x x port e5 3 51 pe6 (hs) i/o c t hs x x x x port e6 4 52 pe7 (hs) i/o c t hs x x x x port e7 5 53 2 39 pb0 i/o c t x ei2 x x port b0 6 54 3 40 pb1 i/o c t x ei2 x x port b1 7 55 4 41 pb2 i/o c t x ei2 x x port b2 8 56 5 42 pb3 i/o c t x ei2 x x port b3 9 1 6 1 pb4 i/o c t x ei3 x x port b4 10 2 pb5 i/o c t x ei3 x x port b5 11 3 pb6 i/o c t x ei3 x x port b6 12 4 pb7 i/o c t x ei3 x x port b7 13 5 7 2 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 14 6 8 3 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 15 7 9 4 pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 16 8 10 5 pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 17 9 11 6 pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 18 10 12 7 pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 19 11 pd6/ain6 i/o c t x x x x x port d6 adc analog input 6 20 12 pd7/ain7 i/o c t x x x x x port d7 adc analog input 7 21 13 13 8 v dda s analog power supply voltage 22 14 14 9 v ssa s analog ground voltage 23 v dd_3 s digital main supply voltage 24 v ss_3 s digital ground voltage 25 15 15 10 pf0/mco i/o c t x ei1 x x port f0 main clock output (f osc /2) 26 16 16 11 pf1/beep i/o c t x ei1 x x port f1 beep signal output 27 17 17 12 pf2 i/o c t x ei1 x x port f2 28 nc not connected
st72334j/n, st72314j/n, st72124j 11/125 29 18 18 13 pf4/ocmp1_a i/o c t x x x x port f4 timer a output compare 1 30 nc not connected 31 19 19 14 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 32 20 20 15 pf7 (hs)/extclk_a i/o c t hs x x x x port f7 timer a external clock source 33 21 21 v dd_0 s digital main supply voltage 34 22 22 v ss_0 s digital ground voltage 35 23 23 16 pc0/ocmp2_b i/o c t x x x x port c0 timer b output compare 2 36 24 24 17 pc1/ocmp1_b i/o c t x x x x port c1 timer b output compare 1 37 25 25 18 pc2 (hs)/icap2_b i/o c t hs x x x x port c2 timer b input capture 2 38 26 26 19 pc3 (hs)/icap1_b i/o c t hs x x x x port c3 timer b input capture 1 39 27 27 20 pc4/miso i/o c t x x x x port c4 spi master in / slave out data 40 28 28 21 pc5/mosi i/o c t x x x x port c5 spi master out / slave in data 41 29 29 22 pc6/sck i/o c t x x x x port c6 spi serial clock 42 30 30 23 pc7/ss i/o c t x x x x port c7 spi slave select (active low) 43 31 pa0 i/o c t x ei0 x x port a0 44 32 pa1 i/o c t x ei0 x x port a1 45 33 pa2 i/o c t x ei0 x x port a2 46 34 31 24 pa3 i/o c t x ei0 x x port a3 47 35 32 25 v dd_1 s digital main supply voltage 48 36 33 26 v ss_1 s digital ground voltage 49 37 34 27 pa4 (hs) i/o c t hs x x x x port a4 50 38 35 28 pa5 (hs) i/o c t hs x x x x port a5 51 39 36 29 pa6 (hs) i/o c t hs x t port a6 52 40 37 30 pa7 (hs) i/o c t hs x t port a7 53 41 38 31 ispsel i must be tied low in user mode. in pro- gramming mode when available, this pin acts as in-situ programming mode se- lection. 54 42 39 32 reset i/o c x x top priority non maskable interrupt (ac- tive low) 55 nc not connected 56 nc 57 43 40 33 v ss_3 s digital ground voltage 58 44 41 34 osc2 these pins connect a parallel-resonant crystal or an external clock source to the on-chip main oscillator. 59 45 42 35 osc1 60 46 43 36 v dd_3 s digital main supply voltage 61 47 44 37 pe0/tdo i/o c t x x x x port e0 sci transmit data out 62 48 1 38 pe1/rdi i/o c t x x x x port e1 sci receive data in 63 nc not connected 64 nc pin n pin name type level port main function (after reset) alternate function tqfp64 sdip56 qfp44 sdip42 input output input output float wpu int ana od pp
st72334j/n, st72314j/n, st72124j 12/125 2.3 register & memory map as shown in the figure 5, the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. the available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of ram, up to 256 bytes of data eeprom and 4 or 8 kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. figure 5. memory map 0000h interrupt & reset vectors hw registers 027fh 0080h short addressing ram (zero page) 16-bit addressing ram 007fh 0200h / 0280h 0bffh reserved 0080h (see table 2) 0c00h ffdfh ffe0h ffffh (see table 6 page 37) 027fh c000h reserved 256 bytes data eeprom 0cffh 0d00h bfffh 00ffh 0100h 01ffh 0200h 8k bytes e000h 16k bytes program short addressing ram (zero page) 0080h 00ffh 01ffh 01ffh 384 bytes ram 512 bytes ram 256 bytes stack or 16-bit addressing ram 256 bytes stack or 16-bit addressing ram 0100h memory program memory
st72334j/n, st72314j/n, st72124j 13/125 register & memory map (cont'd) table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 00h 00h r/w r/w r/w 1) 0003h reserved area (1 byte) 0004h 0005h 0006h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 00h 00h r/w r/w r/w 0007h reserved area (1 byte) 0008h 0009h 000ah port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 00h 00h r/w r/w r/w 1) 000bh reserved area (1 byte) 000ch 000dh 000eh port e pedr peddr peor port e data register port e data direction register port e option register 00h 00h 00h r/w r/w r/w 1) 000fh reserved area (1 byte) 0010h 0011h 0012h port d pddr pdddr pdor port d data register port d data direction register port d option register 00h 00h 00h r/w r/w r/w 1) 0013h reserved area (1 byte) 0014h 0015h 0016h port f pfdr pfddr pfor port f data register port f data direction register port f option register 00h 00h 00h r/w r/w r/w 0017h to 001fh reserved area (9 bytes) 0020h miscr1 miscellaneous register 1 00h r/w 0021h 0022h 0023h spi spidr spicr spisr spi data i/o register spi control register spi status register xxh 0xh 00h r/w r/w read only 0024h to 0028h reserved area (5 bytes) 0029h mcc mccsr main clock control / status register 01h r/w
st72334j/n, st72314j/n, st72124j 14/125 002ah watchdog wdgcr watchdog control register 7fh r/w 002bh crsr clock, reset, supply control / status register 00h r/w 002ch data-eeprom eecsr data-eeprom control/status register 00h r/w 002dh 0030h reserved area (4 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only 2) read only 2) r/w 2) r/w 2) 0040h miscr2 miscellaneous register 2 00h r/w 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00xx xxxx xxh 00h 00h --- 00h read only r/w r/w r/w r/w r/w r/w address block register label register name reset status remarks
st72334j/n, st72314j/n, st72124j 15/125 notes: 1) the bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value. 2) external pin not available. 3) not used in versions without low voltage detector reset. 0058h 006fh reserved area (24 bytes) 0070h 0071h adc adcdr adccsr data register control/status register xxh 00h read only r/w 0072h to 007fh reserved area (14 bytes) address block register label register name reset status remarks
st72334j/n, st72314j/n, st72124j 16/125 2.4 flash program memory 2.4.1 introduction flash devices have a single voltage non-volatile flash memory that may be programmed in-situ (or plugged in a programming tool) on a byte-by- byte basis. 2.4.2 main features n remote in-situ programming (isp) mode n up to 16 bytes programmed in the same cycle n mtp memory (multiple time programmable) n read-out memory protection against piracy 2.4.3 structural organisation the flash program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants. the flash program memory is mapped in the up- per part of the st7 addressing space (f000h- ffffh) and includes the reset and interrupt user vector area . 2.4.4 in-situ programming (isp) mode the flash program memory can be programmed using remote isp mode. this isp mode allows the contents of the st7 program memory to be up- dated using a standard st7 programming tools af- ter the device is mounted on the application board. this feature can be implemented with a minimum number of added components and board area im- pact. an example remote isp hardware interface to the standard st7 programming tool is described be- low. for more details on isp programming, refer to the st7 programming specification. remote isp overview the remote isp mode is initiated by a specific se- quence on the dedicated ispsel pin. the remote isp is performed in three steps: selection of the ram execution mode download of remote isp code in ram execution of remote isp code in ram to pro- gram the user program into the flash remote isp hardware configuration in remote isp mode, the st7 has to be supplied with power (v dd and v ss ) and a clock signal (os- cillator and application crystal circuit for example). this mode needs five signals (plus the v dd signal if necessary) to be connected to the programming tool. this signals are: reset: device reset v ss : device ground power supply ispclk: isp output serial clock pin ispdata: isp input serial data pin ispsel: remote isp mode selection. this pin must be connected to v ss on the application board if any of these pins are used for other purposes on the application, a serial resistor has to be imple- mented to avoid a conflict if the other device forces the signal level. figure 6 shows a typical hardware interface to a standard st7 programming tool. for more details on the pin locations, refer to the device pinout de- scription. figure 6. typical remote isp interface 2.5 program memory read-out protection the read-out protection is enabled through an op- tion bit. for flash devices, when this option is selected, the program and data stored in the flash memo- ry are protected against read-out piracy (including a re-write protection). when this protection option is removed the entire flash program memory is first automatically erased. 1 ispsel v ss reset ispclk ispdata osc1 osc2 v dd st7 he10 connector type to programming tool 10k w c l0 c l1 application 4.7k w 1 xtal
st72334j/n, st72314j/n, st72124j 17/125 2.6 data eeprom 2.6.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back- up for storing data. using the eeprom requires a basic access protocol described in this chapter. 2.6.2 main features n up to 16 bytes programmed in the same cycle n eeprom mono-voltage (charge pump) n chained erase and programming cycles n internal control of the global programming cycle duration n end of programming cycle interrupt flag n wait mode management figure 7. eeprom block diagram eecsr eeprom interrupt falling edge high voltage pump ie lat 0 0000 pgm eeprom reserved detector eeprom memory matrix (1 row = 16 x 8 bits) address decoder data multiplexer 16 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus
st72334j/n, st72314j/n, st72124j 18/125 data eeprom (cont'd) 2.6.3 memory access the data eeprom memory read/write access modes are controlled by the lat bit of the eep- rom control/status register (eecsr). the flow- chart in figure 8 describes these different memory access modes. read operation (lat=0) the eeprom can be read as a normal rom loca- tion when the lat bit of the eecsr register is cleared. in a read cycle, the byte to be accessed is put on the data bus in less than 1 cpu clock cycle. this means that reading data from eeprom takes the same time as reading data from eprom, but this memory cannot be used to exe- cute machine code. write operation (lat=1) to access the write mode, the lat bit has to be set by software (the pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 16 data latches ac- cording to its address. when pgm bit is set by the software, all the previ- ous bytes written in the data latches (up to 16) are programmed in the eeprom cells. the effective high address (row) is determined by the last eep- rom write sequence. to avoid wrong program- ming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously, and an inter- rupt is generated if the ie bit is set. the data eep- rom interrupt request is cleared by hardware when the data eeprom interrupt vector is fetched. note : care should be taken during the program- ming cycle. writing to the same memory location will over-program the memory (logical and be- tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of lat bit. it is not possible to read the latched data. this note is ilustrated by the figure 9. figure 8. data eeprom programming flowchart read mode lat=0 pgm=0 write mode lat=1 pgm=0 read bytes in eeprom area write up to 16 bytes in eeprom area (with the same 12 msb of the address) start programming cycle lat=1 pgm=1 (set by software) lat interrupt generation if ie=1 0 1 cleared by hardware
st72334j/n, st72314j/n, st72124j 19/125 data eeprom (cont'd) 2.6.4 data eeprom and power saving modes wait mode the data eeprom can enter wait mode on ex- ecution of the wfi instruction of the microcontrol- ler. the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle and then enter wait mode. halt mode the data eeprom immediatly enters halt mode if the microcontroller executes the halt in- struction. therefore the eeprom will stop the function in progress, and data may be corrupted. 2.6.5 data eeprom access error handling if a read access occurs while lat=1, then the data bus will not be driven. if a write access occurs while lat=0, then the data on the bus will not be latched. if a programming cycle is interrupted (by software/ reset action), the memory data will not be guar- anteed. figure 9. data eeprom programming cycle lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage eeprom interrupt
st72334j/n, st72314j/n, st72124j 20/125 data eeprom (cont'd) 2.6.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7:3 = reserved, forced by hardware to 0. bit 2 = ie interrupt enable this bit is set and cleared by software. it enables the data eeprom interrupt capability when the pgm bit is cleared by hardware. the interrupt request is automatically cleared when the software enters the interrupt routine. 0: interrupt disabled 1: interrupt enabled bit 1 = lat latch access transfer this bit is set by software. it is cleared by hard- ware at the end of the programming cycle. it can only be cleared by software if pgm bit is cleared. 0: read mode 1: write mode bit 0 = pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is clearedby hardware and an interrupt is generated if the ite bit is set. 0: programming finished or not yet started 1: programming cycle is in progress note : if the pgm bit is cleared during the program- ming cycle, the memory data is not guaranteed. table 3. data eeprom register map and reset values 70 00000ielatpgm address (hex.) register label 76543210 002ch eecsr reset value 00000 ie 0 rwm 0 pgm 0
st72334j/n, st72314j/n, st72124j 21/125 3 central processing unit 3.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 3.2 main features n 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes n two 8-bit index registers n 16-bit stack pointer n low power modes n maskable hardware interrupts n non-maskable software interrupt 3.3 cpu registers the 6 cpu registers shown in figure 10 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 10. cpu registers accumulator x index register y index register stack pointer conditio n code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 87 0 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
st72334j/n, st72314j/n, st72124j 22/125 central processing unit (cont'd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask . this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptable because the i bit is set by hardware when you en- ter it and reset by the iret instruction at the end of the interrupt routine. if the i bit is cleared by soft- ware in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the abit test and brancho, shift and rotate instructions. 70 111hinzc
st72334j/n, st72314j/n, st72124j 23/125 central processing unit (cont'd) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 11). since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. following an mcu reset, or after a reset stack pointer in- struction (rsp), the stack pointer contains its re- set value (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 11. when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 11. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h
st72334j/n, st72314j/n, st72124j 24/125 4 supply, reset and clock management the st72334j/n, st72314j/n and st72124j mi- crocontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. an overview is shown in figure 12. main features n supply manager with main supply low voltage detection (lvd) n reset sequence manager (rsm) n multi-oscillator (mo) 4 crystal/ceramic resonator oscillators 1 external rc oscillator 1 internal rc oscillator n clock security system (css) clock filter backup safe oscillator figure 12. clock, reset and supply block diagram ie d 0 0 0 0 rf rf crsr css wdg f osc css inter rupt lvd low voltage detecto r (lvd) multi- oscillator (mo) from watch dog perip heral osc1 reset vdd vss reset sequen ce manager (rsm) clock filter safe osc clock secur ity syste m (css) main clock controller (mcc) mco f cpu osc2
st72334j/n, st72314j/n, st72124j 25/125 4.1 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v lvdf reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v lvdf reference value for a voltage drop is lower than the v lvdr reference value for power-on in order to avoid a parasitic reset when the mcu starts running and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: v lvdr when v dd is rising v lvdf when v dd is falling the lvd function is illustrated in the figure 13. provided the minimum v dd value (guaranteed for the oscillator frequency) is below v lvdf , the mcu can only be in two modes: under full software control in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices. notes : 1) the lvd allows the device to be used without any exter- nal reset circuitry. 2) three different reference levels are selectable through the option byte according to the application require- ment. lvd application note application software can detect a reset caused by the lvd by reading the lvdrf bit in the crsr register. this bit is set by hardware when a lvd reset is generated and cleared by software (writing zero). figure 13. low voltage detector vs reset v dd v lvdr reset v lvdf hyste resis v lvdhyst
st72334j/n, st72314j/n, st72124j 26/125 4.2 reset sequence manager (rsm) the reset sequence manager includes three re- set sources as shown in figure 15: n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 14: n delay depending on the reset source n 4096 cpu clock cycle delay n reset vector fetch the 4096 cpu clock cycle delay allows the oscil- lator to stabilise and ensures that recovery has taken place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 14. reset sequence phases figure 15. reset block diagram reset delay internal reset 4096 clock cycles fetch vector f cpu counter reset r on v dd watchdog reset lvd reset internal reset
st72334j/n, st72314j/n, st72124j 27/125 reset sequence manager (cont'd) external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. a reset signal originating from an external source must have a duration of at least t pulse in order to be recognized. two reset sequences can be associated with this reset source as shown in figure 16. starting from the external reset pulse recogni- tion, the device reset pin acts as an output that is pulled low during at least t delaymin . figure 16. external reset sequences reset run delay internal reset 4096 clock cycles fetch vector run reset pin external reset source t pulse v dd v lvdf v ddnominal watchdog reset reset run internal reset 4096 clock cycles fetch vector run reset pin external reset source t pulse watchdog reset delay v dd v lvdf v ddnominal short pulse on reset pin long pulse on reset pin t de laymin
st72334j/n, st72314j/n, st72124j 28/125 reset sequence manager (cont'd) internal low voltage detection reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop reset the device reset pin acts as an output that is pulled low when v dd st72334j/n, st72314j/n, st72124j 29/125 reset sequence manager (cont'd) internal watchdog reset the reset sequence generated by a internal watchdog counter overflow is shown in figure 18. starting from the watchdog counter underflow, the device reset pin acts as an output that is pulled low during at least t delaymin . figure 18. watchdog reset sequence reset run delay internal reset 4096 clock cycles fetch vector run reset pin external reset source v dd v lvdf v ddnominal watchdog reset watchdog underflow t de laymin
st72334j/n, st72314j/n, st72124j 30/125 multi-oscillator (mo) the main clock of the st7 can be generated by 7 different sources coming from the multi-oscillator block: n an external source n 4 crystal or ceramic resonator oscillators n 1 external rc oscillator n 1 internal high frequency rc oscillator each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. external clock source the default option byte value selects the ex- ternal clock in the mo block. in this mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground (see figure 19). figure 19. mo external clock crystal/ceramic oscillators this family of oscillators has the advantage of pro- ducing a high accuracy on the main clock of the st7. the selection within a list of 4 oscillators with different frequency ranges has to be done by op- tion byte in order to reduce the consumption. in this mode of the mo block, the resonator and the load capacitances have to be connected as shown in figure 20 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. the loading capacitance values must be adjusted according to the selected oscillator. these oscillators, when selected via the option byte, are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. figure 20. mo crystal/ceramic resonator osc1 osc2 external st7 source osc1 osc2 load capacitances st7 c l1 c l0
st72334j/n, st72314j/n, st72124j 31/125 multi-oscillator (cont'd) external rc oscillator this oscillator allows a low cost solution for the main clock of the st7 using only an external resis- tor and an external capacitor (see figure 21). the selection of the external rc oscillator has to be done by option byte. the frequency of the external rc oscillator (in the range of some mhz.) is fixed by the resistor and the capacitor values: the previous formula shows that in this mo mode, the accuracy of the clock is directly linked to the accuracy of the discrete components. figure 21. mo external rc internal rc oscillator the internal rc oscillator mode is based on the same principle as the external rc oscillator in- cluding the resistance and the capacitance of the device. this mode is the most cost effective one with the drawback of a lower frequency accuracy. its frequency is in the range of several mhz. in this mode, the two oscillator pins have to be tied to ground as shown in figure 22. the selection of the internal rc oscillator has to be done by option byte. figure 22. mo internal rc note: 1) this formula provides an approximation of the frequency with typical r ex and c ex values at v dd =5v. it is given only as design guidelines. f osc ~ 4 r ex .c ex 1) osc1 osc2 st7 c ex r ex osc1 osc2 st7
st72334j/n, st72314j/n, st72124j 32/125 4.3 clock security system (css) the clock security system (css) protects the st7 against main clock problems. to allow the in- tegration of the security features in the applica- tions, it is based on a clock filter control and an in- ternal safe oscillator. the css can be disabled by option byte. 4.3.1 clock filter control the clock filter is based on a clock frequency lim- itation function. this filter function is able to detect and filter high frequency spikes on the st7 main clock. if the oscillator is not working properly (e.g. work- ing at a harmonic frequency of the resonator), the current active oscillator clock can be totally fil- tered, and then no clock signal is available for the st7 from this oscillator anymore. if the original clock source recovers, the filtering is stopped au- tomatically and the oscillator supplies the st7 clock. 4.3.2 safe oscillator control the safe oscillator of the css block is a low fre- quency back-up clock source (see figure 24). if the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the st7 to perform some rescue operations. automatically, the st7 clock source switches back from the safe oscillator if the original clock source recovers. limitation detection the automatic safe oscillator selection is notified by hardware setting the cssd bit of the crsr register. an interrupt can be generated if the cs- sie bit has been previously set. these two bits are described in the crsr register description. figure 23. clock filter function figure 24. safe oscillator function main oscillator clock internal st7 clock main oscillator clock internal st7 clock safe oscillator clock
st72334j/n, st72314j/n, st72124j 33/125 4.4 supply, reset and clock register description clock reset and supply register (crsr) read/write reset value: 000x 000x (00h) bit 7:5 = reserved , always read as 0. bit 4 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared by software (writing zero). see wdgrf flag description for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. bit 3 = reserved , always read as 0. bit 2 = cssie clock security syst . interrupt enable this bit enables the interrupt when a disturbance is detected by the clock security system (cssd bit set). it is set and cleared by software. 0: clock security system interrupt disabled 1: clock security system interrupt enabled when the css is disabled by option byte, the cssie bit has no effect. bit 1 = cssd clock security system detection this bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (f osc ). it is set by hardware and cleared by a read of the crsr register when the original os- cillator recovers. 0: safe oscillator is not active 1: safe oscillator has been activated when the css is disabled by option byte, the cssd bit value is forced to 0. bit 0 = wdgrf watchdog reset flag this bit indicates that the last reset was generat- ed by the watchdog peripheral. it is set by hard- ware (watchdog reset) and cleared by software (writing zero) or a lvd reset (to ensure a stable cleared state of the wdgrf flag when cpu starts). combined with the lvdrf flag information, the flag description is given by the following table. application notes in case the lvdrf flag is not cleared upon anoth- er reset type occurs (extern or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this condition, a watchdog reset can be detect- ed by the software while an external reset not. table 4. clock, reset and supply register map and reset values 70 000 lvd rf 0 css ie css d wdg rf reset sources lvdrf wdgrf external reset pin 0 0 watchdog 0 1 lvd 1 x address (hex.) register label 76543210 002bh crsr reset value 0 0 0 lvdrf x0 cfie 0 cssd 0 wdgrf x
st72334j/n, st72314j/n, st72124j 34/125 4.5 main clock controller (mcc) the mcc block supplies the clock for the st7 cpu and its internal peripherals. it allows to man- age the power saving modes such as the slow and active-halt modes. the whole functionali- ty is managed by the main clock control/status register (mccsr) and the miscellaneous regis- ter 1 (miscr1). the mcc block consists of: a programmable cpu clock prescaler a time base counter with interrupt capability a clock-out signal to supply external devices the prescaler allows to select the main clock fre- quency and is controlled with three bits of the miscr1: cp1, cp0 and sms. the counter allows to generate an interrupt based on a accurate real time clock. four different time bases depending directly on f osc are available. the whole functionality is controlled by four bits of the mccsr register: tb1, tb0, oie and oif. the clock-out capability allows to configure a ded- icated i/o port pin as an f osc /2 clock out to drive external devices. it is controlled by the mco bit in the miscr1 register. when selected, the clock out pin suspends the clock during active-halt mode. figure 25. main clock controller (mcc) block diagram div 2, 4, 8, 16 mcc interrupt div 2 sms cp1 cp0 tb1 tb0 oie oif cpu clock miscr1 programmable divider to cpu and peripher als f osc f cpu mco port function alternate osc2 osc1 mco - - - - 0 0 0 0 mccsr oscillator mcc f osc /2
st72334j/n, st72314j/n, st72124j 35/125 main clock controller (cont'd) miscellaneous register 1 (miscr1) see section 6.2 on page 47. main clock control/status register (mccsr) read/write reset value: 0000 0001 (01h) bit 7:4 = reserved, always read as 0. bit 3:2 = tb1-tb0 time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt allows to exit from active-halt mode. when this bit is set, calling the st7 software halt instruction enters the active-halt power saving mode . bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the csr register. it indicates when set that the main oscillator has measured the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached warning : the bres and bset instructions must not be used on the mccsr register to avoid unin- tentionally clearing the oif bit. table 5. mcc register map and reset values 70 0000tb1tb0oieoif counter prescaler time base tb1 tb0 f osc =8mhz f osc =16mhz 32000 4ms 2ms 0 0 64000 8ms 4ms 0 1 160000 20ms 10ms 1 0 400000 50ms 25ms 1 1 address (hex.) register label 76543210 0029h mccsr reset value 0 0 0 0 tb1 0 tb0 0 oie 0 oif 1
st72334j/n, st72314j/n, st72124j 36/125 5 interrupts & power saving modes 5.1 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the interrupt mapping table and a non- maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 26. the maskable interrupts must be enabled clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec- tion). when an interrupt has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. the i bit of the cc register is set to prevent addi- tional interrupts. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit will be cleared and the main program will resume. priority management by default, the interrupt being serviced cannot be interrupted because the i bit is set by hardware when entering an interrupt routine. if several interrupts are simultaneously pending, a hardware priority defines which one will be serv- iced first (see the interrupt mapping table). non maskable software interrupts this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it will be serviced according to the flowchart on figure 26. interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specific men- tioned interrupts allow the processor to leave the halt low power mode (refer to the aexit from halta column in the interrupt mapping table). external interrupts external interrupt vectors can be loaded in the pc register if the corresponding external interrupt oc- curred and if the i bit is cleared. these interrupts allow the processor to leave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically anded before entering the edge/ level detection block. warning: the type of sensitivity defined in the miscellaneous or interrupt register (if available) applies to the ei source. in case of an anded source (as described on the i/o ports section), a low level on an i/o pin configured as input with in- terrupt, masks the interrupt request even in case of rising-edge sensitivity. peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: the i bit of the cc register is cleared. the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: writing a0o to the corresponding bit in the status register or an access to the status register while the flag is set followed by a read or write of an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed.
st72334j/n, st72314j/n, st72124j 37/125 interrupts (cont'd) figure 26. interrupt processing flowchart table 6. interrupt mapping n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 not used fffah-fffbh 1 mcc css main clock controller time base interrupt or clock security system interrupt mccsr crsr yes fff8h-fff9h 2 ei0 external interrupt port a3..0 n/a fff6h-fff7h 3 ei1 external interrupt port f2..0 fff4h-fff5h 4 ei2 external interrupt port b3..0 fff2h-fff3h 5 ei3 external interrupt port b7..4 fff0h-fff1h 6 not used ffeeh-ffe fh 7 spi spi peripheral interrupts spisr no ffech-ffedh 8 timer a timer a peripheral interrupts tasr ffeah-ffebh 9 timer b timer b peripheral interrupts tbsr ffe8h-ffe9h 10 sci sci peripheral interrupts scisr ffe6h-ffe7h 11 data-eeprom data eeprom interrupt eecsr ffe4h-ffe5h 12 not used ffe2h-ffe3h 13 ffe0h-ffe1h bit i set y n iret y n from reset load pc from interrupt vecto r stack pc, x, a, cc set i bit fetch next instr uction execu te instruction this clears i bit by default restore pc, x, a, cc from stack bit i set y n
st72334j/n, st72314j/n, st72124j 38/125 5.2 power saving modes 5.2.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the the oscil- lator status. figure 27. power saving mode consumption / transitions 5.2.2 halt modes the halt modes are the lowest power consump- tion modes of the mcu. they are entered by exe- cuting the st7 halt instruction (see figure 29). two different halt modes can be distinguished: halt: main oscillator is turned off, active-halt: only main oscillator is running. the decision to enter either in halt or active- halt mode is given by the main oscillator enable interrupt flag (oie bit in cross-mccsr register: see table 7). when entering halt modes, the i bit in the cc register is forced to 0 to enable interrupts. the mcu can exit halt or active-halt modes on reception of an interrupt with exit from halt mode capability or a reset (see table 6 page 37). a 4096 cpu clock cycles delay is performed be- fore the cpu operation resumes (see figure 28). after the start up delay, the cpu resumes opera- tion by servicing the interrupt or by fetching the re- set vector which woke it up. table 7. halt modes selection figure 28. halt /active-halt modes timing overview power consumption wait slow run halt active-halt high low slow wait mccsr oie flag power saving mode entered when halt instruction is executed 0 halt (reset if watchdog enabled) 1 active-halt (no reset if watchdog enabled) halt or active-halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector
st72334j/n, st72314j/n, st72124j 39/125 power saving modes (cont'd) standard halt mode in this mode the main oscillator is turned off caus- ing all internal processing to be stopped, including the operation of the on-chip peripherals. all periph- erals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). the compatibility of watchdog operation with halt mode is configured by the awdghalto option bit of the option byte. the halt instruction when executed while the watchdog system is enabled, can generate a watchdog reset (see dedicated section for more details). when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 4096 cpu cycle delay is used to stabi- lize the oscillator. specific active-halt mode as soon as the interrupt capability of the main os- cillator is selected (oie bit set), the halt instruc- tion will make the device enter a specific active- halt power saving mode instead of the standard halt one. this mode consists of having only the main oscil- lator and its associated counter running to keep a wake-up time base. all other peripherals are not clocked except the ones which get their clock sup- ply from another clock generator (such as external or auxiliary oscillator). the safeguard against staying locked in this ac- tive-halt mode is insured by the oscillator inter- rupt. note: as soon as the interrupt capability of one of the oscillators is selected (oie bit set), entering in active-halt mode while the watchdog is active does not generate a reset. this means that the device cannot to spend more than a defined delay in this power saving mode. figure 29. halt modes flow-chart halt instr uction oscillator 1 0 cpu oscillator periph erals i bit on off 0 off notes: oie bit cpu oscillator peripherals i bit off off 0 off reset exte rnal* y n n y cpu oscillator perip herals on off off interrup t halt activ e-halt main fetch reset vector or service interrupt ** 4096 clock cycles delay cpu oscillator periph erals on on on external interrupt or internal interrupts with exit from halt mode capability * ** before servicing an interrupt, the cc register is pushed on the stack. wat chdog y n enable if wdgha lt bit reset in option byte
st72334j/n, st72314j/n, st72124j 40/125 power saving modes (cont'd) 5.2.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the awfio st7 software instruction. all peripherals remain active. during wait mode, the i bit of the cc register is forced to 0 to enable all interrupts. all other registers and memory re- main unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereup- on the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 30. figure 30. wait mode flow-chart wfi instruction reset interrupt y n n y cpu oscillator periphera ls i bit on on 0 off if exit caused by a reset, a 4096 cpu clock cycle delay is inserted. cpu oscillator peripherals on off* off note: * the peripheral clock is stopped only when exit caused by reset and not by an interrupt. ** before servicing an interrupt, the cc register is pushed on the stack. fetch reset vector or service inter rupt** cpu oscillator peripherals on on on
st72334j/n, st72314j/n, st72124j 41/125 power saving modes (cont'd) 5.2.4 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu )to the available supply voltage. slow mode is controlled by three bits in the miscr1 register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the oscillator frequency can be divid- ed by 4, 8, 16 or 32 instead of 2 in normal operat- ing mode. the cpu and peripherals are clocked at this lower frequency. note : slow-wait mode is activated when enter- ring the wait mode while the device is already in slow mode. figure 31. slow mode: timing diagram for internal cpu clock transitions 00 01 0 1 sms cp1:0 f cpu f osc /8 f osc /4 new frequency request new frequency activ e when osc/4 & osc/8 = 0 normal mode request normal mode active (osc/4, osc/8 stopped) miscr1 registe r
st72334j/n, st72314j/n, st72124j 42/125 6 on-chip peripherals 6.1 i/o ports 6.1.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip pe- ripherals (spi, sci, timers...). an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 6.1.2 functional description each port is associated to 2 main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corre- sponding register bits in ddr and or registers: bit x corresponding to pin x of the port. the same cor- respondence is used for the dr register. the following description takes into account the or register, for specific port which do not provide this register refer to the i/o port implementation section. the generic i/o block diagram is shown on figure 32 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. note1 : writing the dr register modifies the latch value but does not affect the pin status. note2 : when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the ports is con- figured as an output. external interrupt function when an i/o is configured in input with interrupt, an event on this i/o can generate an external in- terrupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is given inde- pendently according to the description mentioned in the miscellaneous register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see interrupt section). if more than one input pins are selected simultane- ously as interrupt source, these are logically and- ed. for this reason if one of the interrupt pins is tied low, it masks the other ones. in case of a floating input with interrupt configura- tion, special cares mentioned in the i/o port imple- mentation section have to be taken. output mode the output configuration is selected by setting the corresponding ddr register bit. in this case, writing the dr register applies this digital value to the i/o pin through the latch. then reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: note: in this mode, interrupt function is disabled. alternate function when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin has to be configured in input mode. in this case, the pin's state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. warning : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. dr push-pu ll open-drain 0v ss vss 1v dd floating
st72334j/n, st72314j/n, st72124j 43/125 i/o ports (cont'd) figure 32. i/o block diagram table 8. port mode options legend :ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (eix) interrupt polarity selection cmos schmitt trigger
st72334j/n, st72314j/n, st72124j 44/125 i/o ports (cont'd) 6.1.3 i/o port implementation the i/o port register configurations are summa- rised as following. standard ports pa5:4, pc7:0, pd7:0, pe7:4, pe1:0, pf7:6, pf4 interrupt ports pa2:0, pb6:4, pb2:0, pf1:0 (with pull-up) pa3, pb7, pb3, pf2 (without pull-up) switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 33 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 33. interrupt i/o port state transition true open drain ports pa7:6 table 9. port configuration mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr floating input 0 open drain (high sink ports) 1 01 pull-up/floating interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or port pin name input output or = 0 or = 1 or = 0 or = 1 port a pa7:6 floating true open-drain pa5:4 floating pull-up open drain push-pull pa3 floating floating interrupt open drain push-pull pa2:0 floating pull-up interrupt open drain push-pull port b pb7, pb3 floating floating interrupt open drain push-pull pb6:4, pb2:0 floating pull-up interrupt open drain push-pull port c pc7:0 floating pull-up open drain push-pull port d pd7:0 floating pull-up open drain push-pull port e pe7:4, pe1:0 floating pull-up open drain push-pull port f pf7:6, pf4 floating pull-up open drain push-pull pf2 floating floating interrupt open drain push-pull pf1:0 floating pull-up interrupt open drain push-pull
st72334j/n, st72314j/n, st72124j 45/125 i/o ports (cont'd) 6.1.4 register description data register (dr) port x data register pxdr with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register pxor with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = o[7:0] option register 8 bits. for specific i/o pins, this register is not implement- ed. in this case the ddr register is enough to se- lect the i/o pin configuration. the or register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. each bit is set and cleared by software. input mode: 0: floating input 1: pull-up input with or without interrupt output mode: 0: output open drain (with p-buffer unactivated) 1: output push-pull 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0
st72334j/n, st72314j/n, st72124j 46/125 i/o ports (cont'd) table 10. i/o port register map and reset values notes: 1) the bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value. address (hex.) register label 76543210 reset value of all io port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 1) 0004h pcdr msb lsb 0005h pcddr 0006h pcor 0008h pbdr msb lsb 0009h pbddr 000ah pbor 1) 000ch pedr msb lsb 000dh peddr 000eh peor 1) 0010h pddr msb lsb 0011h pdddr 0012h pdor 1) 0014h pfdr msb lsb 0015h pfddr 0016h pfor
st72334j/n, st72314j/n, st72124j 47/125 6.2 miscellaneous registers the miscellaneous registers allow control over several different features such as the external in- terrupts or the i/o alternate functions. 6.2.1 i/o port interrupt sensitivity description the external interrupt sensitivity is controlled by the isxx bits of the miscr1 miscellaneous regis- ter. this control allows to have two fully independ- ent external interrupt source sensitivities. each external interrupt source can be generated on four different events on the pin: n falling edge n rising edge n falling and rising edge n falling edge and low level to guarantee correct functionality, the sensitivity bits in the miscr1 register must be modified only when the i bit of the cc register is set to 1 (inter- rupt masked). see i/o port register and miscella- neous register descriptions for more details on the programming. 6.2.2 i/o port alternate functions the miscr registers manage four i/o port miscel- laneous alternate functions: n main clock signal (f cpu ) output on pf0 n a beep signal output on pf1 (with 3 selectable audio frequencies) n spi pin configuration: ss pin internal control to use the pc7 i/o port function while the spi is active. these functions are described in detail in the sec- tion 6.2.3 miscellaneous registers description.
st72334j/n, st72314j/n, st72124j 48/125 miscellaneous registers (cont'd) 6.2.3 miscellaneous registers description miscellaneous register 1 (miscr1) read/write reset value: 0000 0000 (00h) bit 7:6 = is1[1:0] ei2 and ei3 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: ei2 (port b3..0) and ei3 (port b7..4). these 2 bits can be written only when the i bit of the cc register is set to 1 (interrupt disabled). bit 5 = mco main clock out selection this bit enables the mco alternate function on the i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f osc /2 on i/o port) note : to reduce power consumption, the mco function is not active in active-halt mode. bit 4:3 = is2[1:0] ei0 and ei1 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts:- ei0 (port a3..0) and ei1 (port f2..0). these 2 bits can be written only when the i bit of the cc register is set to 1 (interrupt disabled). bit 2:1 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc /2 1: slow mode. f cpu is given by cp1, cp0 see low power consumption mode and mcc chapters for more details. 70 is11 is10 mco is21 is20 cp1 cp0 sms is11 is10 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge cp1 cp0 f cpu in slow mode 00f osc /4 10f osc /8 01f osc /16 11f osc /32
st72334j/n, st72314j/n, st72124j 49/125 miscellaneous registers (cont'd) miscellaneous register 2 (miscr2) read/write reset value: 0000 0000 (00h) bit 7:6 = reserved must always be cleared bit 5:4 = bc[1:0] beep control these 2 bits select the pf1 pin beep capability. the beep output signal is available in active- halt mode but has to be disabled to reduce the consumption. bit 3:2 = reserved must always be cleared bit 1 = ssm ss mode selection it is set and cleared by software. 0: normal mode - ss uses information coming from the ss pin of the spi. 1: i/o mode, the spi uses the information stored into bit ssi. bit 0 = ssi ss internal mode this bit replaces pin ss of the spi when bit ssm is set to 1. (see spi description). it is set and cleared by software. table 11. miscellaneous register map and reset values 70 - - bc1 bc0 - - ssm ssi bc1 bc0 beep mode with f osc =16mhz 0 0 off 0 1 ~2-khz output beep signal ~50% duty cycle 1 0 ~1-khz 1 1 ~500-hz address (hex.) register label 76543210 0020h miscr1 reset value is11 0 is10 0 mco 0 is21 0 is20 0 cp1 0 cp0 0 sms 0 0040h miscr2 reset value 0 0 bc1 0 bc0 000 ssm 0 ssi 0
st72334j/n, st72314j/n, st72124j 50/125 6.3 watchdog timer (wdg) 6.3.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter's contents before the t6 bit be- comes cleared. 6.3.2 main features n programmable timer (64 increments of 12288 cpu cycles) n programmable reset n reset (if watchdog activated) after a halt instruction or when the t6 bit reaches zero n hardware watchdog selectable by option byte n watchdog reset indicated by status flag (in versions with safe reset option only) 6.3.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. figure 34. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 12288 t1 t2 t3 t4 t5
st72334j/n, st72314j/n, st72124j 51/125 watchdog timer (cont'd) the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 12 .watchdog timing (fcpu = 8 mhz)): the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an imme- diate reset the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 12.watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. 6.3.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the device-specific option byte descrip- tion. 6.3.5 low power modes 6.3.6 interrupts none. 6.3.7 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). status register (sr) read/write reset value*: 0000 0000 (00h) bit 0 = wdogf watchdog flag . this bit is set by a watchdog reset and cleared by software or a power on/off reset. this bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: no watchdog reset occurred 1: watchdog reset occurred * only by software and power on/off reset note: this register is not used in versions without lvd reset. cr register initial value wdg timeout period (ms) max ffh 98.304 min c0h 1.536 mode description wait no effect on watchdog. halt immediate reset generation as soon as the halt instruction is executed if the watchdog is activated (wdga bit is set). 70 wdga t6 t5 t4 t3 t2 t1 t0 70 - - - - - - - wdogf
st72334j/n, st72314j/n, st72124j 52/125 watchdog timer (cond't) table 13. watchdog timer register map and reset values address (hex.) register label 76543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1
st72334j/n, st72314j/n, st72124j 53/125 6.4 16-bit timer 6.4.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. 6.4.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt n input capture functions with 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 35. *note: some external pins are not available on all devices. refer to the device pin out description. when reading an input signal which is not availa- ble on an external pin, the value will always be `1'. 6.4.3 functional description 6.4.3.1 counter the principal block of the programmable timer is a 16-bit free running increasing counter and its as- sociated 16-bit registers: counter registers counter high register (chr) is the most sig- nificant byte (msb). counter low register (clr) is the least sig- nificant byte (lsb). alternate counter registers alternate counter high register (achr) is the most significant byte (msb). alternate counter low register (aclr) is the least significant byte (lsb). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (overflow flag), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 14 clock control bits. the value in the counter register re- peats every 131.072, 262.144 or 524.288 internal processorclock cycles depending on the cc1 and cc0 bits.
st72334j/n, st72314j/n, st72124j 54/125 16-bit timer (cont'd) figure 35. timer block diagram mcu-peripheral interface counter alternate register output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8 high 16 16 16 16 cr1 cr2 sr 6 16 888 8 88 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc1 cc0 16 bit free running counter
st72334j/n, st72314j/n, st72124j 55/125 16-bit timer (cont'd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the msb first, then the lsb value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the msb several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the lsb of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: toie bit of the cr1 register is set and i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. this feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 6.4.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit determines the type of level transition on the external clock pin ext- clk that will trigger the free running counter. the counter is synchronised with the falling edge of the internal cpu clock. at least four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock frequen- cy must be less than a quarter of the cpu clock frequency. lsb is buffered read msb at t0 read lsb returns the buffered lsb value at t0 at t0 + d t other instructions beginning of the sequence sequence completed
st72334j/n, st72314j/n, st72124j 56/125 16-bit timer (cont'd) figure 36. counter timing diagram, internal clock divided by 2 figure 37. counter timing diagram, internal clock divided by 4 figure 38. counter timing diagram, internal clock divided by 8 cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register overflow flag tof fffc fffd 0000 0001 cpu clock internal reset timer clock counter register overflow flag tof cpu clock internal reset timer clock counter register overflow flag tof fffc fffd 0000
st72334j/n, st72314j/n, st72124j 57/125 16-bit timer (cont'd) 6.4.3.3 input capture in this section, the index, i , may be 1 or 2. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). ic i register is a read-only register. the active transition is software programmable through the iedg i bit of the control register (cr i ). timing resolution is one count of the free running counter: ( f cpu /(cc1.cc0) ). procedure: to use the input capture function select the follow- ing in the cr2 register: select the timer clock (cc1-cc0) (see table 14 clock control bits). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input). and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from both the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input). when an input capture occurs: icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 40). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 2. after reading the ic i hr register, transfer of input capture data is inhibited until the ic i lr register is also read. 3. the ic i r register always contains the free run- ning counter value which corresponds to the most recent input capture. 4. the 2 input capture functions can be used together even if the timer also uses the output compare mode. 5. in one pulse mode and pwm mode only the input capture 2 can be used. 6. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture process. 7. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the icie bit is set. 8. the tof bit can be used with interrupt in order to measure event that go beyond the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr
st72334j/n, st72314j/n, st72124j 58/125 16-bit timer (cont'd) figure 39. input capture block diagram figure 40. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge.
st72334j/n, st72314j/n, st72124j 59/125 16-bit timer (cont'd) 6.4.3.4 output compare in this section, the index, i , may be 1 or 2. this function can be used to control an output waveform or indicating when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: assigns pins with a programmable value if the ocie bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the free run- ning counter each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/(cc1.cc0) ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i function. select the timer clock (cc1-cc0) (see table 14 clock control bits). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset and stays low until valid compares change it to a high level). a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = desired output compare period (in sec- onds) f cpu = internal clock frequency presc = timer prescaler factor (2, 4 or 8 de- pending on cc1-cc0 bits, see table 14 clock control bits) clearing the output compare interrupt request is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the clock is divided by 2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 42). this behaviour is the same in opm or pwm mode. when the clock is divided by 4, 8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r register value plus 1 (see figure 43). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. ms byte ls byte oc i roc i hr oc i lr d oc i r= d t * f cpu presc
st72334j/n, st72314j/n, st72124j 60/125 16-bit timer (cont'd) figure 41. output compare block diagram figure 42. output compare timing diagram, internal clock divided by 2 figure 43. output compare timing diagram, internal clock divided by 4 output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin internal cpu clock timer clock counter output compare register output compare flag (ocfi) ocmpi pin (olvli=1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter output compare register compare register latch ocfi and ocmpi pin (olvli=1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf
st72334j/n, st72314j/n, st72124j 61/125 16-bit timer (cont'd) 6.4.3.5 forced compare in this section i may represent 1 or 2. the following bits of the cr1 register are used: when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in both one pulse mode and pwm mode. 6.4.3.6 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in section 6.4.3.7). 2. select the following in the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. set the opm bit. select the timer clock cc1-cc0 (see table 14 clock control bits). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the val- ue fffdh is loaded in the ic1r register. when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 44). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. the icf1 bit is set when an active edge occurs and can generate an interrupt if the icie bit is set. 3. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 4. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 5. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 6. when the one pulse mode is used oc1r is dedicated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an output waveform because the level olvl2 is dedicated to the one pulse mode. folv2 folv1 olvl2 olvl1 event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set
st72334j/n, st72314j/n, st72124j 62/125 figure 44. one pulse mode timing example figure 45. pulse width modulation mode timing example counter .... fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter 34e2 fffc fffd fffe 2ed0 2ed1 2ed2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1
st72334j/n, st72314j/n, st72124j 63/125 16-bit timer (cont'd) 6.4.3.7 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register, and so these functionality can not be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal. 2. load the oc1r register with the value corre- sponding to the length of the pulse if (olvl1=0 and olvl2=1). 3. select the following in the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. set the pwm bit. select the timer clock (cc1-cc0) (see table 14 clock control bits). if olvl1=1 and olvl2=0 the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = desired output compare period (in sec- onds) f cpu = internal clock frequency presc = timer prescaler factor (2, 4 or 8 de- pending on cc1-cc0 bits, see table 14 clock control bits) the output compare 2 event causes the counter to be initialized to fffch (see figure 45). notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. therefore the input capture 1 function is inhib- ited but the input capture 2 is available. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. oc i r value = t * f cpu presc -5 counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set
st72334j/n, st72314j/n, st72124j 64/125 16-bit timer (cont'd) 6.4.4 low power modes 6.4.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc register is reset (rim instruction). mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with aexit from halt modeo capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with aexit from halt modeo capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no
st72334j/n, st72314j/n, st72124j 65/125 16-bit timer (cont'd) 6.4.6 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1
st72334j/n, st72314j/n, st72124j 66/125 16-bit timer (cont'd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer re- mains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer re- mains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc1-cc0 clock control. the value of the timer clock depends on these bits: table 14. clock control bits bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the free running counter. 0: a falling edge triggers the free running counter. 1: a rising edge triggers the free running counter. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu /4 0 0 f cpu /2 0 1 f cpu /8 1 0 external clock (where available) 11
st72334j/n, st72314j/n, st72124j 67/125 16-bit timer (cont'd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) regis- ter. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred.to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st72334j/n, st72314j/n, st72124j 68/125 16-bit timer (cont'd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st72334j/n, st72314j/n, st72124j 69/125 16-bit timer (cont'd) table 15. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timer a: 34 timer b: 44 ichr1 reset value msb - ------ lsb - timer a: 35 timer b: 45 iclr1 reset value msb - ------ lsb - timer a: 36 timer b: 46 ochr1 reset value msb - ------ lsb - timer a: 37 timer b: 47 oclr1 reset value msb - ------ lsb - timer a: 3e timer b: 4e ochr2 reset value msb - ------ lsb - timer a: 3f timer b: 4f oclr2 reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ichr2 reset value msb - ------ lsb - timer a: 3d timer b: 4d iclr2 reset value msb - ------ lsb -
st72334j/n, st72314j/n, st72124j 70/125 6.5 serial peripheral interface (spi) 6.5.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 6.5.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = fcpu/2. n four programmable master bit rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 6.5.3 general description the spi is connected to external devices through 4 alternate pins: miso: master in slave out pin mosi: master out slave in pin sck: serial clock pin ss: slave select pin a basic example of interconnections between a single master and a single slave is illustrated on figure 46. the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 49) but master and slave must be programmed with the same timing mode. figure 46. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit
st72334j/n, st72314j/n, st72124j 71/125 serial peripheral interface (cont'd) figure 47. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spe spr2 mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - -- -- it request master control
st72334j/n, st72314j/n, st72124j 72/125 serial peripheral interface (cont'd) 6.5.4 functional description figure 46 shows the serial peripheral interface (spi) block diagram. this interface contains 3 dedicated registers: a control register (cr) a status register (sr) a data register (dr) refer to the cr, sr and dr registers in section 6.5.7for the bit definitions. 6.5.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure select the spr0 & spr1 bits to define the se- rial clock baud rate (see cr register). select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 49). the ss pin must be connected to a high level signal during the complete byte transmit se- quence. the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: the spif bit is set by hardware an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a write or a read of the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read.
st72334j/n, st72314j/n, st72124j 73/125 serial peripheral interface (cont'd) 6.5.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0 & spr1 bits is not used for the data transfer. procedure for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 49. the ss pin must be connected to a low level signal during the complete byte transmit se- quence. clear the mstr bit and set the spe bit to as- sign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware an interrupt is generated if spie bit is set and i bit in ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2. a write or a read of the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 6.5.4.6). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (see section 6.5.4.4).
st72334j/n, st72314j/n, st72124j 74/125 serial peripheral interface (cont'd) 6.5.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 49, shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the first clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 48). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the second clock transition. this pin must be toggled high and low between each byte transmitted (see figure 48). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 48. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 vr02131a
st72334j/n, st72314j/n, st72124j 75/125 serial peripheral interface (cont'd) figure 49. data clock timing diagram cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) vr02131b msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit
st72334j/n, st72314j/n, st72124j 76/125 serial peripheral interface (cont'd) 6.5.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a oread collisiono will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 50). figure 50. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read sr read dr write dr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read sr read dr note: writing in dr register in- stead of reading in it do not reset wcol bit read sr or then then then
st72334j/n, st72314j/n, st72124j 77/125 serial peripheral interface (cont'd) 6.5.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: the modf bit is set and an spi interrupt is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spe and mstr bits may be restored to their original state during or af- ter this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 6.5.4.6 overrun condition an overrun condition occurs, when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al.
st72334j/n, st72314j/n, st72124j 78/125 serial peripheral interface (cont'd) 6.5.4.7 single master and multimaster configurations there are two types of spi systems: single master system multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 51). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 51. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu
st72334j/n, st72314j/n, st72124j 79/125 serial peripheral interface (cont'd) 6.5.5 low power modes 6.5.6 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the i-bit in the cc reg- ister is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with aexit from halt modeo capability. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf yes no
st72334j/n, st72314j/n, st72124j 80/125 serial peripheral interface (cont'd) 6.5.7 register description control register (cr) read/write reset value: 0000xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in the sr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 6.5.4.5 master mode fault). 0: i/o port connected to pins 1: spi alternate functions connected to pins the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. bit 5 = spr2 divider enable . this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 16. 0: divider by 2 enabled 1: divider by 2 disabled bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 6.5.4.5 master mode fault). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software.used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. these 2 bits have no effect in slave mode. table 16. serial peripheral baud rate 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /2 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1
st72334j/n, st72314j/n, st72124j 81/125 serial peripheral interface (cont'd) status register (sr) read only reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (see figure 50). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 6.5.4.5 master mode fault). an spi interrupt can be gen- erated if spie=1 in the cr register. this bit is cleared by a software sequence (an access to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3-0 = unused. data i/o register (dr) read/write reset value: undefined the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. warning: a write to the dr register places data directly into the shift register for transmission. a write to the the dr register returns the value lo- cated in the buffer and not the contents of the shift register (see figure 47 ). 70 spif wcol - modf - - - - 70 d7 d6 d5 d4 d3 d2 d1 d0
st72334j/n, st72314j/n, st72124j 82/125 serial peripheral interface (cont'd) table 17. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spisr reset value spif 0 wcol 00 modf 00000
st72334j/n, st72314j/n, st72124j 83/125 6.6 serial communications interface (sci) 6.6.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. 6.6.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n dual baud rate generator systems n independently programmable transmit and receive baud rates up to 250k baud. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: address bit (msb) idle line n muting functionfor multiprocessor configurations n separate enable bits for transmitter and receiver n three error detection flags: overrun error noise error frame error n five interrupt sources with flags: transmit data register empty transmission complete receive data register full idle line received overrun error detected 6.6.3 general description the interface is externally connected to another device by two pins (see figure 53): tdo: transmit data output. when the transmit- ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena- bled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through this pins, serial data is transmitted and re- ceived as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete. this interface usestwo types of baud rate generator: a conventional type for commonly-used baud rates, an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies.
st72334j/n, st72314j/n, st72124j 84/125 serial communications interface (cont'd) figure 52. sci block diagram wake up unit receive r control sr transmit control tdre tc rdrf idle or nf fe - sci control interrupt cr1 r8 t8 - m wake - -- received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data regist er) dr transmit ter clock receiver clock receiver rate trans mitter rate brr scp1 f cpu control control scp0sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conven tional baud rate generator sbk rwu re te ilie rie tcie tie cr2
st72334j/n, st72314j/n, st72124j 85/125 serial communications interface (cont'd) 6.6.4 functional description the block diagram of the serial control interface, is shown in figure 52. it contains 6 dedicated reg- isters: two control registers (cr1 & cr2) a status register (sr) a baud rate register (brr) an extended prescaler receiver register (erpr) anextendedprescaler transmitter register (etpr) refer to the register descriptions in section 6.6.7for the definitions of each bit. 6.6.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the cr1 register (see figure 52). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of a1os followed by the start bit of the next frame which contains data. a break character is interpreted on receiving a0os for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra a1o bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 53. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra '1' data frame break frame start bit extra '1' data frame next data frame next data frame
st72334j/n, st72314j/n, st72124j 86/125 serial communications interface (cont'd) 6.6.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the cr1 reg- ister. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the dr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 52). procedure select the m bit to define the word length. select the desired baud rate using the brr and the etpr registers. set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. access the sr register and write the data to send in the dr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register the tdre bit is set by hardware and it indicates: the tdr register is empty. the data transfer is beginning. the next data can be written in the dr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the dr register stores the data in the tdr register and which is copied in the shift regis- ter at the end of the current transmission. when no transmission is taking place, a write in- struction to the dr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shift register with a break character. the break frame length depends on the m bit (see figure 53). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the dr.
st72334j/n, st72314j/n, st72124j 87/125 serial communications interface (cont'd) 6.6.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the cr1 reg- ister. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, dr register consists in a buffer (rdr) between the in- ternal bus and the received shift register (see fig- ure 52). procedure select the m bit to define the word length. select the desired baud rate using the brr and the erpr registers. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the sr register 2. a read to the dr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the spi han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when a overrun error occurs: the or bit is set. the rdr content will not be lost. the shift register will be overwritten. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the sr register followed by a dr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: the nf is set at the rising edge of the rdrf bit. data is transferred from the shift register to the dr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a sr register read operation followed by a dr register read operation. framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. a break is received. when the framing error is detected: the fe bit is set by hardware data is transferred from the shift register to the dr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a sr register read operation followed by a dr register read operation.
st72334j/n, st72314j/n, st72124j 88/125 serial communications interface (cont'd) figure 54. sci baud rate and extended prescaler block diagram transmi tter receiver etpr erpr exte nded prescaler receiver rate control exte nded prescaler transmitte r rate control extended prescaler clock clock receiver rate transmit ter rate brr scp1 f cpu control control scp0sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conventional baud rate generator exte nded receiver prescaler register exte nded trans mitter prescale r register
st72334j/n, st72314j/n, st72124j 89/125 serial communications interface (cont'd) 6.6.4.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp0 & scp1 bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct0, sct1 & sct2 bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr0,scr1 & scr2 bits) all this bits are in the brr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 19200 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 6.6.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry standard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 54. the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the erpr or the etpr register. note: the extended prescaler is activated by set- ting the etpr or erpr register to a value other than zero. the baud rates are calculated as fol- lows: with: etpr = 1,..,255 (see etpr register) erpr = 1,.. 255 (see erpr register) 6.6.4.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupt are inhibited. a muted receiver may be awakened by one of the following two ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a a1o as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. tx = (32 * pr) * tr f cpu rx = (32 * pr) * rr f cpu tx = 16 * etpr f cpu rx = 16 * erpr f cpu
st72334j/n, st72314j/n, st72124j 90/125 serial communications interface (cont'd) 6.6.5 low power modes 6.6.6 interrupts the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corre- sponding enable control bit is set and the i-bit in the cc register is reset (rim instruction). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/receiving until halt mode is exited. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie yes no overrrun error detected or yes no idle line detected idle ilie yes no
st72334j/n, st72314j/n, st72124j 91/125 serial communications interface (cont'd) 6.6.7 register description status register (sr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie =1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note : data will not be transferred to the shift regis- ter as long as the tdre bit is not reset. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: transmission is not complete 1: transmission is complete bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred into the dr register. an interrupt is generated if rie=1 in the cr2 register. it is cleared by hardware when re=0 or by a software sequence (an access to the sr register followed by a read to the dr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the cr2 register. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). this bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the cr2 reg- ister. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift register will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr regis- ter). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. bit 0 = unused. 70 tdre tc rdrf idle or nf fe -
st72334j/n, st72314j/n, st72124j 92/125 serial communications interface (cont'd) control register 1 (cr1) read/write reset value: undefined bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the sr register. bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the sr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the sr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the sr register. bit 3 = te transmitter enable. this bit enables the transmitter and assigns the tdo pin to the alternate function. it is set and cleared by software. 0: transmitter is disabled, the tdo pin is back to the i/o port configuration. 1: transmitter is enabled note: during transmission, a a0o pulse on the te bit (a0o followed by a1o) sends a preamble after the current word. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled, it resets the rdrf, idle, or, nf and fe bits of the sr register. 1: receiver is enabled and begins searching for a start bit. bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to a1o and then to a0o, the transmitter will send a break word at the end of the current word. 70 r8 t8 - m wak e - - - 70 tie tcie rie ilie te re rwu sbk
st72334j/n, st72314j/n, st72124j 93/125 serial communications interface (cont'd) data register (dr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 52). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 52). baud rate register (brr) read/write reset value: 00xx xxxx (xxh) bit 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bit 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. note: this tr factor is used only when the etpr fine tuning factor is equal to 00h; otherwise, tr is replaced by the etpr dividing factor. bit 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. note: this rr factor is used only when the erpr fine tuning factor is equal to 00h; otherwise, rr is replaced by the erpr dividing factor. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividi ng factor sct2 sct1 sct0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 rr dividi ng factor scr2 scr1 scr0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1
st72334j/n, st72314j/n, st72124j 94/125 serial communications interface (cont'd) extended receive prescaler division register (erpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bit 7:1 = erpr[7:0] 8-bit extended receive pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 54) is divided by the binary factor set in the erpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (etpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bit 7:1 = etpr[7:0] 8-bit extended transmit pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 54) is divided by the binary factor set in the etpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. table 18. sci register map and reset values 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 address (hex.) register label 76543210 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 00 0051h scidr reset value msb xxxxxxx lsb x 0052h scibrr reset value sog 00 vpol x 2fhdet x hvsel x vcordis x clpinv x blkinv x 0053h scicr1 reset value r8 x t8 x0 m x wake x000 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0055h scipbrr reset value msb 0000000 lsb 0 0057h scipbrt reset value msb 0000000 lsb 0
st72334j/n, st72314j/n, st72124j 95/125 6.7 8-bit a/d converter (adc) 6.7.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 6.7.2 main features n 8-bit conversion n up to 16 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 56. 6.7.3 functional description 6.7.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 55. recommended ext. connections figure 56. adc block diagram st7 px.x/ainx v dda v ssa v dd 0.1pf r ain v ain ch2 ch1 ch3 coco 0 adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux r adc c sample d2 d1 d3 d7 d6 d5 d4 d0 adcdr 4 div 2 f adc f cpu hold control
st72334j/n, st72314j/n, st72124j 96/125 8-bit a/d converter (adc) (cont'd) 6.7.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the con- version result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdr register. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 6.7.3.3 a/d conversion phases the a/d conversion is based on two conversion phases as shown in figure 57: n sample capacitor loading [duration: t load ] during this phase, the v ain input voltage to be measured is loaded into the c sample sample capacitor. n a/d conversion [duration: t conv ] during this phase, the a/d conversion is computed (8 successive approximations cycles) and the c sample sample capacitor is disconnected from the analog input pin to get the optimum a/d conversion accuracy. while the adc is on, these two phases are contin- uously repeated. at the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 6.7.3.4 software procedure refer to the control/status register (csr) and data register (dr) in section 6.7.6 for the bit definitions and to figure 57 for the timings. adc configuration the total duration of the a/d conversion is 12 adc clock periods (1/f adc =2/f cpu ). the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: select the ch[3:0] bits to assign the analog channel to convert. adc conversion in the csr register: set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conver- sion of the selected channel. when a conversion is complete the coco bit is set by hardware. no interrupt is generated. the result is in the dr register and remains valid until the next conversion has ended. a write to the csr register (with adon set) aborts the current conversion, resets the coco bit and starts a new conversion. figure 57. adc conversion timings 6.7.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed and between single shot conversions.. 6.7.5 interrupts none mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d converter requires a stabilisation time before accurate conversions can be performed. adccsr write adon coco bit set t load t conv operation hold control
st72334j/n, st72314j/n, st72124j 97/125 8-bit a/d converter (adc) (cont'd) 6.7.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete 1: conversion can be read from the dr register bit 6 = reserved. must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4 = reserved. must always be cleared. bit 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *note : the number of pins and the channel selection var- ies according to the device. refer to the device pinout. data register (dr) read only reset value: 0000 0000 (00h) bit 7:0 = d[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. note : reading this register reset the coco flag. 70 coco 0 adon 0 ch3 ch2 ch1 ch0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d7 d6 d5 d4 d3 d2 d1 d0
st72334j/n, st72314j/n, st72124j 98/125 8-bit a/d converter (adc) (cont'd) table 19. adc register map and reset values address (hex.) register label 76543210 0070h adcdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0071h adccsr reset value coco 00 adon 00 ch3 0 ch2 0 ch1 0 ch0 0
st72334j/n, st72314j/n, st72124j 99/125 7 instruction set 7.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 20. st7 addressing mode overview note 1. at the time the instruction is executed, the program counter (pc) points to the instruction follow- ing jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) +1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
st72334j/n, st72314j/n, st72124j 100/125 st7 addressing modes (cont'd) 7.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 7.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the the operand value. 7.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 7.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 7.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st72334j/n, st72314j/n, st72124j 101/125 st7 addressing modes (cont'd) 7.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 21. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 7.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only functio n clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative
st72334j/n, st72314j/n, st72124j 102/125 7.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf
st72334j/n, st72314j/n, st72124j 103/125 instruction groups (cont'd) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned >
st72334j/n, st72314j/n, st72124j 104/125 instruction groups (cont'd) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z
st72334j/n, st72314j/n, st72124j 105/125 8 electrical characteristics 8.1 absolute maximum ratings this product contains devices for protecting the in- puts against damage due to high static voltages, however it is advisable to take normal precautions to avoid applying any voltage higher than the specified maximum rated voltages. for proper operation it is recommended that v i and v o be higher than v ss and lower than v dd . reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (v dd or v ss ). power considerations . the average chip-junc- tion temperature, t j , in celsius can be obtained from: t j = ta + pd x rthja where: t a = ambient temperature. rthja =package thermal resistance (junction-to ambient). p d =p int +p port . p int =i dd xv dd (chip internal power). p port =port power dissipation determined by the user) note: stresses above those listed as aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating con- ditions for extended periods may affect device reliability. general warning: directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or the program counter is corrupted (by an expected change to the i/o configuration). to guarantee safe op- eration, this connection has to be done through a pull-up or pull-down resistor (10k w typical). thermal characteristics symbol ratings value unit v dd -v ss supply voltage 6.5 v v dda -v ssa analog reference voltage v dda >v ss 6.5 v |v dd_i -v dd_j | |v dd_i -v dda | max. variations (power line) 50 mv |v ss_i -v ss_j | |v ss_i -v ssa | max. variations (ground line) 50 mv v in input voltage v ss - 0.3 to v dd + 0.3 v v out output voltage v ss - 0.3 to v dd + 0.3 v esd esd susceptibility 2000 v i vdd_i total current into v dd_i (source) 150 ma i vss_i total current out of v ss_i (sink) 150 symbol ratings value unit r thja package thermal resistance tqfp64 sdip56 tqfp44 sdip42 60 tbd tbd tbd c/w t jmax max. junction temperature 150 c t stg storage temperature range -65 to +150 c pd power dissipation 500 mw
st72334j/n, st72314j/n, st72124j 106/125 8.2 recommended operating conditions figure 58. f osc maximum operating frequency versus v dd supply voltage 3) notes: 1) unless otherwise specified, typical data are based on t a =25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2) a/d operation and resonator oscillator start-up are not guaranteed below 1mhz. 3) operating conditions t a =-40 to +85 c. the shaded area is outside the recommended operating range; device func- tionality is not guaranteed under these conditions. general symbol parameter conditi ons min typ max unit v dd supply voltage see figure 58 3.0 5.5 v f osc resonator oscillator frequency v dd 3.5v 1 16 mhz v dd 3.0v 1 8 external clock source v dd 3.5v 0 2) 16 v dd 3.0v 0 2) 8 t a ambient temperature range 1 suffix version 0 70 c 6 suffix version -40 85 7 suffix version -40 105 3 suffix version -40 125 f osc [mhz] supply voltage [v] 16 8 4 1 0 2.5 3 3.5 4 4.5 5 5.5 functionali ty not guaran teed in this area functi onality not guaranteed in this area with resona tor functiona lity guaranteed in this area funct ionality not guaran teed in this area for temperatu re higher than 85 c
st72334j/n, st72314j/n, st72124j 107/125 8.3 dc electrical characteristics recommended operating conditions with t a =-40 to +85 o c, v dd -v ss =5v unless otherwise specified. 8.4 general timing characteristics notes: 1) unless otherwise specified, typical data are based on t a =25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2) cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss , all peripherals switched off; clock input (osc1) driven by external square wave. 3) all i/o pins in input mode with a static value at v dd or v ss , all peripherals switched off; clock input (osc1) driven by external square wave. 4) all i/o pins in input mode with a static value at v dd or v ss , lvd disabled. 5) data based on characterization results, not tested in production. 6) d t inst is the number of t cpu to finish the current instruction execution. symbol parameter conditio ns min typ 1) max unit i dd supply current in run mode 2) f osc = 4 mhz, f cpu = 2 mhz f osc = 8 mhz, f cpu = 4 mhz f osc = 16 mhz, f cpu = 8 mhz tbd ma supply current in slow mode 2) f osc = 4 mhz, f cpu = 125 khz f osc = 8 mhz, f cpu = 250 khz f osc = 16 mhz, f cpu = 500 khz tbd supply current in wait mode 3) f osc = 4 mhz, f cpu = 2 mhz f osc = 8mhz, f cpu = 4 mhz f osc = 16mhz, f cpu = 8 mhz tbd supply current in slow wait mode 3) f osc = 4 mhz, f cpu = 2 mhz f osc = 8 mhz, f cpu = 250 khz f osc = 16 mhz, f cpu = 500 khz tbd supply current in halt mode 4) i load = 0ma (current on i/os) tbd m a v rm data retention mode 5) halt mode 2 v symbol parameter conditi ons min typ max unit t inst instruction time 2 12 t cpu t irt interrupt reaction time t irt = d t inst +10 6) 10 22 t cpu
st72334j/n, st72314j/n, st72124j 108/125 8.5 i/o port characteristics recommended operating conditions with t a =-40 to +85 o c and 4.5vv ih v in v dd 5 ma negative 6) :v ext v dd tbd negative: v ext st72334j/n, st72314j/n, st72124j 109/125 8.6 supply, reset and clock characteristics 8.6.1 supply manager recommended operating conditions with t a =-40 to +85 o c and voltage are referred to v ss unless otherwise specified. 8.6.2 reset sequence manager recommended operating conditions with t a =-40...+85 o c and 4.5vv ih v in st72334j/n, st72314j/n, st72124j 110/125 supply, reset and clock characteristics (cont'd) notes: 1) unless otherwise specified, typical data are based on t a =25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2) these data are based on typical r smax . the oscillator selection can be optimized in terms of supply current with high quality resonator. 3) r smax is the equivalent serial resistance of the crystal or ceramic resonator. 4) data based on design simulation and/or technology characteristics, not tested in production. 5) data based on characterization results, not tested in production. 6) in this condition, the capacitor to be considered is the global parasitic capacitor. in this case, the rc oscillator frequen- cy tuning has to be done by trying out several resistor values. crystal and ceramic resonator oscillators symbol parameter condition s min typ 1) max unit f osc oscillator frequency 2) low speed resonator medium-low speed resonator medium-high speed resonator high speed resonator 1 >2 >4 >8 2 4 8 16 mhz c li low speed load medium-low speed capacitance medium-high speed high speed r smax =200 w 3) r smax =200 w 3) r smax =200 w 3) r smax =100 w 3) 38 4) 32 4) 18 4) 15 4) 47 39 22 18 56 4) 46 4) 26 4) 21 4) pf i dd low speed supply medium-low speed current medium-high speed high speed 150 200 400 700 700 5) 700 5) 750 5) 1100 5) m a t start oscillator start-up time depends on resonator quality. a typical value is 10ms external rc oscillato r symbol parameter condition s min 4) typ 1) max unit f osc external rc oscillator frequency v dd =5v 114 4) mhz r ex oscillator external resistance 10 33 47 4) k w c ex oscillator external capacitance 0 6) 47 470 4) pf i dd supply current 525 750 5) m a internal rc oscillator symbol parameter condition s min typ 1) max unit f osc internal rc oscillator frequency v dd =5.5v 3.50 4.25 5.00 mhz v dd =3.0v 3.35 4.10 4.85 i dd supply current 500 750 5) m a clock security system (css) symbol parameter conditions min typ 1) max unit f sfosc safe oscillator frequency v dd =5.5v 250 340 430 khz v dd =3.0v 190 260 330 f cfl clock filter frequency limitation 30 mhz i dd supply current 150 350 5) m a
st72334j/n, st72314j/n, st72124j 111/125 8.7 memory and peripheral characteristics recommended operating conditions with t a =-40 to +85 o c and 3v st72334j/n, st72314j/n, st72124j 112/125 memory and peripheral characteristics (cont'd) figure 59. spi master timing diagram cpha=0, cpol=0 2) notes: 1) data based on characterization results, not tested in production. 2) measurement points are v ol ,v oh ,v il and v ih in the spi timing diagram. spi serial peripheral interface ref. symbol parameter condition value 1) unit min max f spi spi frequency master slave 1/128 dc 1/4 1/2 f cpu 1t spi spi clock period master slave 4 2 t cpu 2t lead enable lead time slave 120 ns 3t lag enable lag time slave 120 ns 4t spi_h clock (sck) high time master slave 100 90 ns 5t spi_l clock (sck) low time master slave 100 90 ns 6t su data set-up time master slave 100 100 ns 7t h data hold time (inputs) master slave 100 100 ns 8t a access time (time to data active from high impedance state) slave 0 120 ns 9t dis disable time (hold time to high im- pedance state) 240 ns 10 t v data valid master (before capture edge) slave (after enable edge) 0.25 120 t cpu ns 11 t hold data hold time (outputs) master (before capture edge) slave (after enable edge) 0.25 0 t cpu ns 12 t rise rise time (20% v dd to 70% v dd ,c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 13 t fall fall time (70% v dd to 20% v dd ,c l = 200pf) outputs: sck,mosi,miso inputs: sck,mosi,miso,ss 100 100 ns m s 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 d7-out d6-out d0-out d7-in d6-in d0-in vr000109
st72334j/n, st72314j/n, st72124j 113/125 memory and peripheral characteristics (cont'd) figure 60. spi master timing diagram cpha=0, cpol=1 1) figure 61. spi master timing diagram cpha=1, cpol=0 1) figure 62. spi master timing diagram cpha=1, cpol=1 1) note: 1) measurement points are v ol ,v oh ,v il and v ih in the spi timing diagram. 1 67 10 11 12 13 ss (input) sck (output) miso mosi (input) (outpu t) 4 5 vr000110 d7-out d6-out d0-out d7-in d6-in d0-in 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (outpu t) 5 4 vr000107 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck (output) miso mosi (input) (output) 4 5 vr000108 d7-out d6-out d0-out d7-in d6-in d0-in
st72334j/n, st72314j/n, st72124j 114/125 memory and peripheral characteristics (cont'd) measurement points are v ol ,v oh ,v il and v ih in the spi timing diagram figure 63. spi slave timing diagram cpha=0, cpol=0 1) figure 64. spi slave timing diagram cpha=0, cpol=1 1) figure 65. spi slave timing diagram cpha=1, cpol=0 1) figure 66. spi slave timing diagram cpha=1, cpol=1 1) note: 1) measurement points are v ol ,v oh ,v il and v ih in the spi timing diagram. 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (outpu t) 5 4 (input) 2 3 8 9 high-z vr000113 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (outpu t) 54 (input) 2 3 8 9 high-z vr000114 d7-in d6-in d0-in d7-out d6-out d0-out 1 6 7 10 11 12 13 ss (input) sck miso mosi (input) (output) 5 4 (input) 2 3 8 9 high-z vr000111 d7-out d6-out d0-out d7-in d6-in d0-in 1 67 10 11 12 13 ss (input) sck miso mosi (input) (output) 54 (input) 2 3 8 9 high-z d7-out d6-out d0-out d7-in d6-in d0-in vr000112
st72334j/n, st72314j/n, st72124j 115/125 memory and peripheral characteristics (cont'd) note: 1) unless otherwise specified, typical data are based on t a =25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. sci serial communication interface symbol parameter conditions typ 1) unit f tx or f rx communication frequency (precision vs. standard ~0.16%) f cpu =8mhz standard mode tr (resp.rr)=64, pr=13 tr (resp.rr)=16, pr=13 tr (resp.rr)= 8, pr=13 tr (resp.rr)= 4, pr=13 tr (resp.rr)= 2, pr=13 tr (resp.rr)= 8, pr= 3 tr (resp.rr)= 1, pr=13 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230,77 hz extended mode etpr (resp.erpr) = 13 ~38461.54 see astandard i/o port pinso description for more details.
st72334j/n, st72314j/n, st72124j 116/125 memory and peripheral characteristics (cont'd) notes: 1) unless otherwise specified, typical data are based on t a =25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2) data based on characterization results, not tested in production. 3) tested in production at t a =25 c, characterized over the whole temperature range. 4) adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6 m a and the effect on the adc accuracy is a loss of 1 lsb for each 10k w increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input -at5vv dd supply, and worst case temperature. adc analog to digital converter (8-bit) symbol parameter conditions min typ 1) max unit f adc analog control frequency v dd =v dda =5v 4 2) mhz |tue| total unadjusted error 4) t a =25 c,v dd =v dda =5v, 3) f cpu =8mhz,f adc =4mhz 1 lsb oe offset error 4) -0.5 0.5 ge gain error 4) -0.5 0.5 |dle| differential linearity error 4) 0.5 |ile| integral linearity error 4) 0.5 v ain conversion range voltage v ssa v dda v i adc a/d conversion supply current f cpu =8mhz, f adc =4mhz v dd =v dda =5v 1ma t stab stabilization time after adc enable 1 m s t load sample capacitor loading time 1 4 m s 1/f adc t conv hold conversion time 2 8 m s 1/f adc r ain external input resistor 15 2) k w r adc internal input resistor 1.5 k w c sample sample capacitor 6 pf oe ge 1 lsb (ideal) 1lsb ideal v dda v ssa 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line tue =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. oe =offset error: deviation between the first actual transition and the first ideal one. ge =gain error: deviation between the last ideal transition and the last actual one. dle =differential linearity error: maximum devia- tion between actual steps and the ideal one. ile =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) tue dle ile (3) v dda v ssa
st72334j/n, st72314j/n, st72124j 117/125 9 general information 9.1 packages 9.1.1 package mechanical data figure 67. 64-pin thin quad flat package figure 68. 56-pin shrink plastic dual in-line package, 600-mil width dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.00 0.472 e 16.00 0.630 e1 14.00 0.551 e3 12.00 0.472 e 0.80 0.031 k 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 nd 16 ne 16 l1 l k dim. mm inches min typ max min typ max a 6.35 0.250 a1 0.38 0.015 a2 3.18 4.95 0.125 0.195 b 0.41 0.016 b2 0.89 0.035 c 0.20 0.38 0.008 0.015 d 50.29 53.21 1.980 2.095 e 15.01 0.591 e1 12.32 14.73 0.485 0.580 e 1.78 0.070 ea 15.24 0.600 eb 17.78 0.700 l 2.92 5.08 0.115 0.200 number of pins n56 pdip56s
st72334j/n, st72314j/n, st72124j 118/125 packages (cont'd) figure 69. 44-pin thin quad flat package figure 70. 42-pin shrink plastic dual in-line package, 600-mil width dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 e 0.80 0.031 k 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 44 b c l1 l k dim. mm inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.46 0.56 0.018 0.022 b2 1.02 1.14 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.600 0.630 e1 12.70 13.72 14.48 0.500 0.540 0.570 e 1.78 0.070 ea 15.24 0.600 eb 18.54 0.730 ec 0.00 1.52 0.000 0.060 l 2.54 3.30 3.56 0.100 0.130 0.140 number of pins n42 pdip42s
st72334j/n, st72314j/n, st72124j 119/125 packages (cont'd) 9.1.2 user-supplied tqfp64 adaptor / socket to solder the tqfp64 device directly on the appli- cation board, or to solder a socket for connecting the emulator probe, the application board should provide the footprint described in figure 71. this footprint allows both configurations: n direct tqfp64 soldering n yamaichi ic149-064-008-s5* socket soldering to plug either the emulator probe or an adaptor board with an tqfp64 clamshell socket. * not compatible with tqfp64 package. figure 71. tqfp64 device and emulator probe compatible footprint table 22. suggested list of tqfp64 socket types package / probe adaptor / socket reference socket type tqfp64 enplas otq-64-0.8-02 open top yamaichi ic51-0644-1240.ks-14584 clamshell emu probe yamaichi ic149-064-008-s5 smc detai l e b * sk: plastic socket overall dimensions. dim mm inches min typ max min typ max b 0.35 0.45 0.50 0.014 0.018 0.020 e 20.80 0.819 e1 14.00 0.551 e3 11.90 12.00 12.10 0.468 0.472 0.476 e 0.75 0.80 0.85 0.029 0.031 0.033 sk* 26 1.023 number of pins n 64 (4x16) e e1 e3 e e1 e3 socket sk sk
st72334j/n, st72314j/n, st72124j 120/125 packages (cont'd) 9.1.3 user-supplied tqfp44 adaptor / socket to solder the tqfp44 device directly on the appli- cation board, or to solder a socket for connecting the emulator probe, the application board should provide the footprint described in figure 72. this footprint allows both configurations: n direct tqfp44 soldering n yamaichi ic149-044-*52-s5 socket soldering to plug either the emulator probe or an adaptor board with an tqfp44 clamshell socket. figure 72. tqfp44 device and emulator probe compatible footprint table 23. suggested list of tqfp44 socket types package / probe adaptor / socket reference socket type tqfp44 enplas otq-44-0.8-04 open top yamaichi ic51-0444-467-ks-11787 clamshell tqfp44 emu probe yamaichi ic149-044-*52-s5 smc detai l e b * sk: plastic socket overall dimensions. dim mm inches min typ max min typ max b 0.35 0.45 0.50 0.014 0.018 0.020 e 13.40 0.527 e1 10.00 0.394 e3 7.95 8.00 8.05 0.313 0.315 0.317 e 0.75 0.80 0.85 0.029 0.031 0.033 sk* 24.2 0.953 number of pins n 44 (4x11) e e1 e3 e e1 e3 socket sk sk
st72334j/n, st72314j/n, st72124j 121/125 9.2 device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (rom). flash devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be con- figured by the customer using the option bytes while the rom devices are factory-configured. 9.2.1 option bytes the two option bytes allow the hardware configu- ration of the microcontroller to be selected. the option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 4programming tool). the default contents of the flash is fixed to ffh. this means that all the op- tions have a1o as their default value. in masked rom devices, the option bytes are fixed in hardware by the rom code. user option byte 1 bit 7:2 = reserved, must always be 1. bit 1 = 56/42 package configuration . this option bit allows to configure the device ac- cording to the package. 0: 42 and 44 pin. 1: 56 and 64 pin. bit 0 = fmp full memory protection. this option bit enables or disables external access to the internal program memory (read-out protec- tion). clearing this bit causes the erasing (to 00h) of the whole memory (including the option byte). 0: program memory not read-out protected 1: program memory read-out protected user option byte 2 bit 7 = cfc clock filter control on/off this option bit enables or disables the clock filter (cf) features. 0: clock filter enabled 1: clock filter disabled bit 6:4 = osc[2:0] oscillator selection these three option bits can be used to select the main oscillator as shown in table 24. table 24. main oscillator configuration bit 3:2 = lvd[1:0] low voltage detection selection these option bits enable the lvd block with a se- lected threshold as shown in table 25. table 25. lvd threshold configuration bit 1 = wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode bit 0 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) 70 1 1 1 1 1 1 56/42 fmp 70 cfc osc2 osc1 osc0 lvd1 lvd0 wdg halt wdg sw selected oscillator osc2 osc1 osc0 external clock (stand-by) 1 1 1 internal rc 1 1 0 external rc 101 100 low speed resonator 0 1 1 medium-low speed resonator 0 1 0 medium-high speed resonator 0 0 1 high speed resonator 0 0 0 configuratio n lvd1 lvd0 lvd off 1 1 highest voltage threshold (v dd ~5v) 1 0 medium voltage threshold (f osc 16mhz) 0 1 lowest voltage threshold (f osc 8mhz) 0 0
st72334j/n, st72314j/n, st72124j 122/125 device configuration and ordering information (cont'd) 9.2.2 transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .s19 format generated by the development tool. all un- used bytes must be set to ffh. the selected options are communicated to stmi- croelectronics using the correctly completed op- tion list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 73. rom factory coded device types figure 74. flash user programmable device types device package temp. range xxx / code name (defined by stmicroelectronics) 1 = standard 0 to +70 c 6 = industrial -40 to +85 c 7 = automotive -40 to +125 c 3 = automotive -40 to +125 c b = plastic dip t = plastic tqfp st72334j2, st72334j4, st72334n2, st72334n4, st72314j2, st72314j4, st72314n2, st72314n4, st72124j2 device package temp. range code name (defined by stmicroelectronics) 1 = standard 0 to +70 c 6 = industrial -40 to +85 c 7 = automotive -40 to +125 c 3 = automotive -40 to +125 c b = plastic dip t = plastic tqfp st72c334j2, st72c334j4, st72c334n2, st72c334n4, st72c314j2, st72c314j4, st72c314n2, st72c314n4, st72c124j2 xxx
st72334j/n, st72314j/n, st72124j 123/125 microcontroller option list customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................. address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................. contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................. phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................. reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................. stmicroelectronics references device: [ ] st72334j2 [ ] st72314j2 [ ] st72124j2 [ ] st72334j4 [ ] st72314j4 [ ] st72334n2 [ ] st72314n2 [ ] st72334n4 [ ] st72314n4 package: [ ] tqfp64 [ ] sdip56 [ ] tqfp44 [ ] sdip42 temperature range: [ ] 0 cto+70 c []-40 cto+85 c[]-40 c to + 125 c clock source selection: [ ] resonator: [ ] lp: low power resonator (1 to 2 mhz) [ ] mp: medium power resonator (2 to 4 mhz) [ ] ms: medium speed resonator (4 to 8 mhz) [ ] hs: high speed resonator (8 to 16 mhz) [ ] rc network: [ ] internal [ ] external [ ] external clock clock security system: [ ] disabled [ ] enabled watchdog selection: [ ] software activation [ ] hardware activation halt when watchdog on: [ ] reset [ ] no reset readout protection: [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] enabled: [ ] highest threshold (4.30v/4.05v) [ ] medium threshold (3.90v/3.65v) [ ] lowest threshold (3.35v/3.10v) comments : . . . ............................................................. supply operating range in the application: . . . . . . . . . . . . ............................ notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................... signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................................... date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................
st72334j/n, st72314j/n, st72124j 124/125 10 summary of changes description of the changes between the current release of the specification and the previous one. revision main changes date 1.0 new chapter to compare st72334 versus st72331 (section 2.1 on page 6) correction of the address of the crsr register to 2bh instead of 25h (table 4 page 33) correction of port a pin name column in table 9 page 44 (pa2:0 instead of pa3:0) correction of miscr2 register description (section 6.2.3 on page 48) correction of the flash and data eeprom programming time (section 8.7 on page 111) correction of the tqfp44 socket proposal (table 23 page 120) more information on the fmp option bit (section 9.2.1 on page 121) added .s19 format in transfer of code (section 9.2.2 on page 122) correction of the microcontroller option list (section 9.2.2 on page 122) history page added (section 10 on page 124) sept-99
st72334j/n, st72314j/n, st72124j 125/125 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain sweden - switzerland - united kingdom - u.s.a. http:// www.st.com

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